The present invention is related to the field of integrated circuit design and, more particularly, to the circuit design of arithmetic and logic units.
There are two principal techniques of implementing integrated circuit logic to calculate arithmetic and logic functions. One technique is serial design. In this technique logic stages are serially connected so that the results of one stage are fed to another stage in a chain until the results of desired function are completely determined. Serial design occupies the smallest amount of integrated circuit area for a given function; however, the resulting functional unit is typically slow in most applications. Each stage must wait for the results of the previous stage to become available and each additional bit of width adds one or two more gate delays to the time for the results to appear.
The second technique is parallel lookahead design. In this technique logic blocks are connected in parallel. The higher order logic blocks do not have to wait for the lower order logic blocks to complete their operation. The higher order blocks receive their input signals nearly simultaneously with the lower order blocks. The output of earlier stages are fed forward in parallel to later stages which combine the outputs of earlier stages. This design has the highest performance for a given function; however, the parallel design occupies a lot of space on an integrated circuit.
The differences between these two design techniques have become more apparent as busses in microprocessors have become wider. Present busses having 32 bits render serial design far too slow. However, the space occupied by a parallel lookahead design is a significant factor in the layout of an integrated circuit. Busses of 64 bits make the space problem even more acute.
The present invention solves, or substantially mitigates, this design problem so that arithmetic and logic circuits can be designed with a circuit layout occupying far less space than a functionally equivalent parallel lookahead design. Nonetheless, operating speeds are close to that of parallel lookahead designs.